120 lines
3.1 KiB
Verilog
120 lines
3.1 KiB
Verilog
module top;
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reg signed [7:0] neg = -2;
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reg signed [7:0] m1 = -1;
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reg signed [7:0] zero = 0;
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reg signed [7:0] one = 1;
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reg signed [7:0] pos = 2;
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reg signed [7:0] pose = 2;
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reg signed [7:0] poso = 3;
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reg signed [7:0] res;
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wire signed [7:0] neg_pose = neg**pose;
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wire signed [7:0] neg_poso = neg**poso;
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wire signed [7:0] m1_pose = m1**pose;
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wire signed [7:0] m1_poso = m1**poso;
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wire signed [7:0] zero_pos = zero**pos;
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wire signed [7:0] one_pos = one**pos;
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wire signed [7:0] pos_pos = pos**pos;
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wire signed [7:0] neg_zero = neg**zero;
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wire signed [7:0] m1_zero = m1**zero;
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wire signed [7:0] zero_zero = zero**zero;
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wire signed [7:0] one_zero = one**zero;
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wire signed [7:0] pos_zero = pos**zero;
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wire signed [7:0] neg_neg = neg**m1;
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wire signed [7:0] m1_nege = m1**neg;
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wire signed [7:0] m1_nego = m1**m1;
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wire signed [7:0] zero_neg = zero**m1;
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wire signed [7:0] one_neg = one**m1;
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wire signed [7:0] pos_neg = pos**m1;
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reg pass;
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initial begin
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pass = 1'b1;
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#1;
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/* Positive exponent. */
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if (neg_pose !== 4) begin
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$display("Failed neg**pos even, got %d", neg_pose);
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pass = 1'b0;
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end
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if (neg_poso !== -8) begin
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$display("Failed neg**pos odd, got %d", neg_poso);
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pass = 1'b0;
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end
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if (m1_pose !== 1) begin
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$display("Failed -1**pos even, got %d", m1_pose);
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pass = 1'b0;
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end
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if (m1_poso !== -1) begin
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$display("Failed -1**pos odd, got %d", m1_poso);
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pass = 1'b0;
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end
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if (zero_pos !== 0) begin
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$display("Failed 0**pos, got %d", zero_pos);
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pass = 1'b0;
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end
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if (one_pos !== 1) begin
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$display("Failed 1**pos, got %d", one_pos);
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pass = 1'b0;
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end
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if (pos_pos !== 4) begin
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$display("Failed 1**pos, got %d", pos_pos);
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pass = 1'b0;
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end
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/* Zero exponent. */
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if (neg_zero !== 1) begin
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$display("Failed neg**0, got %d", neg_zero);
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pass = 1'b0;
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end
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if (m1_zero !== 1) begin
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$display("Failed -1**0, got %d", m1_zero);
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pass = 1'b0;
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end
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if (zero_zero !== 1) begin
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$display("Failed 0**0, got %d", zero_zero);
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pass = 1'b0;
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end
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if (one_zero !== 1) begin
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$display("Failed 1**0, got %d", one_zero);
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pass = 1'b0;
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end
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if (pos_zero !== 1) begin
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$display("Failed pos**0, got %d", pos_zero);
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pass = 1'b0;
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end
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/* Negative exponent. */
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if (neg_neg !== 0) begin
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$display("Failed neg**neg got %d", neg_neg);
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pass = 1'b0;
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end
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if (m1_nege !== 1) begin
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$display("Failed -1**neg (even) got %d", m1_nege);
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pass = 1'b0;
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end
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if (m1_nego !== -1) begin
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$display("Failed -1**neg (odd) got %d", m1_nego);
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pass = 1'b0;
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end
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if (zero_neg !== 'sbx) begin
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$display("Failed 0**neg (odd) got %d", zero_neg);
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pass = 1'b0;
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end
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if (one_neg !== 1) begin
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$display("Failed 1**neg got %d", one_neg);
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pass = 1'b0;
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end
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if (pos_neg !== 0) begin
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$display("Failed pos**neg got %d", pos_neg);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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