30 lines
474 B
Verilog
30 lines
474 B
Verilog
module main;
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reg [1:0] a, b;
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reg flag;
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(* ivl_combinational *)
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always @(a, b)
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flag = a && b;
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(* ivl_synthesis_off *)
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initial begin
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a = 1;
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b = 0;
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#1 if (flag !== 0) begin
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$display("FAILED -- a=%b, b=%b, flag=%b", a, b, flag);
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$finish;
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end
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b = 2;
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#1 if (flag !== 1) begin
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$display("FAILED -- a=%b, b=%b, flag=%b", a, b, flag);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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