22 lines
386 B
Verilog
22 lines
386 B
Verilog
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module main;
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initial begin
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int idx;
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for (idx = 1 ; idx < 5 ; ) begin
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$display("... %02d", idx);
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idx += 1;
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end
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if (idx !== 5) begin
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$display("FAILED -- idx=%0d", idx);
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$finish;
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end
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idx = 2;
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for ( ; idx < 5 ; ) begin
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$display("... %02d", idx);
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idx += 1;
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end
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$display("PASSED");
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$finish;
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end
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endmodule // main
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