67 lines
939 B
Verilog
67 lines
939 B
Verilog
module dut(input EN1, input I1, output O1,
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input EN2, input I2, output O2);
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assign O1 = EN1 ? I1 : 1'bz;
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assign O2 = EN2 ? I2 : 1'bz;
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specify
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(I1 => O1) = (2);
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(EN1 *> O1) = (4);
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(I2 => O2) = (3);
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(EN2 *> O2) = (4);
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endspecify
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endmodule
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module test();
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reg EN1;
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reg EN2;
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reg I1;
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reg I2;
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tri O;
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pulldown(O);
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dut dut(EN1, I1, O, EN2, I2, O);
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reg failed = 0;
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initial begin
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$monitor($time,,EN1,,I1,,EN2,,I2,,O);
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EN1 = 0;
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EN2 = 0;
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#4;
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#0 if (O !== 0) failed = 1;
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I1 = 1;
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I2 = 1;
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#1;
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EN1 = 1;
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#3;
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#0 if (O !== 0) failed = 1;
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#1;
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#0 if (O !== 1) failed = 1;
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I1 = 0;
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#1;
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#0 if (O !== 1) failed = 1;
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#1;
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#0 if (O !== 0) failed = 1;
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EN1 = 0;
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EN2 = 1;
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#3;
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#0 if (O !== 0) failed = 1;
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#1;
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#0 if (O !== 1) failed = 1;
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I2 = 0;
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#2;
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#0 if (O !== 1) failed = 1;
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#1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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