20 lines
380 B
Verilog
20 lines
380 B
Verilog
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//
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// This tests that the parameter and localparam show up in the vcd dump.
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//
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module main;
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parameter [3:0] foo = 4'd5;
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localparam [3:0] bar = 7;
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parameter real PI = 3.14;
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wire [3:0] bat = foo + bar;
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wire real tau = 2.0 * PI;
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initial begin
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$dumpfile("work/br_gh156.vcd");
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$dumpvars(0, main);
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#1 $finish;
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end
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endmodule // main
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