33 lines
396 B
Verilog
33 lines
396 B
Verilog
module test();
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function parity(input bit_array[3:0]);
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integer i;
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begin
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parity = 0;
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for (i = 0; i < 4; i = i + 1) begin
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$display("%b", bit_array[i]);
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parity ^= bit_array[i];
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end
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end
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endfunction
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reg a[3:0];
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reg p;
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initial begin
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a[0] = 1;
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a[1] = 0;
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a[2] = 1;
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a[3] = 1;
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p = parity(a);
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if (p === 1)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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