23 lines
395 B
Verilog
23 lines
395 B
Verilog
module test;
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reg passed;
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logic y;
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always_comb begin
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y = 1'b0;
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end
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initial begin
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passed = 1'b1;
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if (y !== 1'bx) begin
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$display("FAILED: expected 1'bx, got %b", y);
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passed = 1'b0;
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end
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#1;
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if (y !== 1'b0) begin
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$display("FAILED: expected 1'b0, got %b", y);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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