22 lines
342 B
Verilog
22 lines
342 B
Verilog
module main;
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integer x;
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initial begin
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x = $copy_test(1);
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if (x !== 1) begin
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$display("FAILED -- x == %b (should be 1)", x);
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$finish;
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end
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x = $copy_test(8);
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if (x !== 8) begin
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$display("FAILED -- x == %b (should be 8)", x);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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