36 lines
717 B
Verilog
36 lines
717 B
Verilog
module partsel(inout wire [1:0] part);
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assign part = 2'bz;
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endmodule
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module test();
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wire [3:0] full;
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partsel sel(full[1:0]);
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initial begin
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#1 $peek(full);
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#0 $display("display : %b %b", full, sel.part);
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#1 $force(full);
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#1 $peek(full);
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#0 $display("display : %b %b", full, sel.part);
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#1 $release(full);
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#0 $display("display : %b %b", full, sel.part);
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#1 $force(full);
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#1 $peek(full);
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#0 $display("display : %b %b", full, sel.part);
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#1 $poke(full);
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#1 $peek(full);
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#0 $display("display : %b %b", full, sel.part);
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#1 $release(full);
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#0 $display("display : %b %b", full, sel.part);
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#1 $poke(full);
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#1 $peek(full);
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#0 $display("display : %b %b", full, sel.part);
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end
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endmodule
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