49 lines
732 B
Verilog
49 lines
732 B
Verilog
module top();
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reg [3:0] a;
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reg [4:0] b;
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wire [8:0] y;
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functest uut(a, b, y);
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initial begin
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a = 3'b101;
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b = 4'b0101;
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#1;
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if (y == 8'b10100101)
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$display("PASSED");
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else
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$display("FAILED y = %b", y);
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end
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endmodule // top
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module functest (
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operand_a,
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operand_b,
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result_y
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);
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input [3:0] operand_a;
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input [4:0] operand_b;
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output [8:0] result_y;
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function [8:0] concat_this;
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input [3:0] op_s;
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input [4:0] op_l;
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concat_this = {op_s, op_l};
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endfunction
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reg [8:0] result_y_wire;
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always @ (operand_a or operand_b) begin
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result_y_wire = concat_this(operand_a, operand_b);
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end
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assign result_y = result_y_wire;
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endmodule
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