32 lines
593 B
Verilog
32 lines
593 B
Verilog
module top ();
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reg [31:0] din;
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wire [31:0] dout;
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test t(din, dout);
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initial begin
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din = 5;
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#1;
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$display("dout=%d", dout);
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if (dout == 5)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule // top
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module test ( din, dout);
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input [31:0] din;
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output [31:0] dout;
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buff #(1) d0_1 ( .in(din[0:0]), .out(dout[0:0]));
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buff #(32) d0_32 ( .in(din[31:0]), .out(dout[31:0]));
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endmodule // test
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module buff (out, in);
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parameter SIZE=1;
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output [SIZE-1:0] out;
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input [SIZE-1:0] in;
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assign out[SIZE-1:0] = in[SIZE-1:0];
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endmodule // buff
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