25 lines
399 B
Verilog
25 lines
399 B
Verilog
module top();
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wire out1, out2;
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child c1(1, 0, out1);
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child c2(1, 1, out2);
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initial begin
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#1;
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if (out1 !== 0)
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$display("FAILED -- out1 !== 0");
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else if (out2 !== 1)
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$display("FAILED -- out2 !== 1");
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else
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$display("PASSED");
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end
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endmodule // top
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module child(in1, in2, out);
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input in1, in2;
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output out;
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assign out = in1 & in2;
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endmodule // child
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