30 lines
487 B
Verilog
30 lines
487 B
Verilog
module top();
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tri tdo, tdo_out;
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reg tdo_oe;
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assign tdo = tdo_oe ? tdo_out : 1'bz;
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assign tdo_out = 1'b1;
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// Check undriven value is Z
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initial begin
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tdo_oe = 0;
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#1;
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if (tdo !== 1'bz) begin
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$display("FAILED -- tdo not z when tdo_oe = 0");
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$finish;
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end
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tdo_oe = 1;
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#1;
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#1;
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if (tdo !== 1'b1) begin
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$display("FAILED -- tdo not tdo_out when tdo_oe = 0");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // top
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