60 lines
1.5 KiB
Verilog
60 lines
1.5 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Validate continuous adds in assignment..dependent on always + working
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//
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// $Log: wireadd1.v,v $
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// Revision 1.2 2001/05/03 05:45:37 ka6s
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// Lets try this again
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//
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//
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module main;
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reg globvar;
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reg [3:0] var1,var2,var3;
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wire [3:0] var3a;
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reg error;
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assign var3a = var1 + var2;
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always @( var1 or var2)
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var3 = var1 + var2 ;
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initial
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begin
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error = 0;
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for ( var1 = 4'b0; var1 != 4'hf; var1 = var1 + 1)
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for ( var2 = 4'b0; var2 != 4'hf; var2 = var2 + 1)
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begin
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#1 ;
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if(var3 !== var3a)
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error = 1;
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#1;
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end
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if(error == 0)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule // main
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