30 lines
541 B
Verilog
30 lines
541 B
Verilog
module top;
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reg [1:0] lv, rv;
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real rl;
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reg res;
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string st;
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wire r1, r2, r3, r4, r5, r6, r7, r8;
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assign r1 = rl ==? rv;
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assign r2 = lv ==? rl;
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assign r3 = rl !=? rv;
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assign r4 = lv !=? rl;
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assign r1 = st ==? rv;
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assign r2 = lv ==? st;
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assign r3 = st !=? rv;
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assign r4 = lv !=? st;
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initial begin
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res = rl ==? rv;
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res = lv ==? rl;
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res = rl !=? rv;
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res = lv !=? rl;
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res = st ==? rv;
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res = lv ==? st;
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res = st !=? rv;
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res = lv !=? st;
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$display("FAILED");
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end
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endmodule
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