112 lines
2.6 KiB
Verilog
112 lines
2.6 KiB
Verilog
`timescale 1ns/10ps
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module top;
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reg pass;
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real rise, fall, delay, base, diff;
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reg in, ctl;
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wire out, outif0;
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buf #(rise, fall) dut(out, in);
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bufif0 #(rise, fall) dutif0(outif0, in, ctl);
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// Check that the buffer output has the correct value and changed at the
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// correct time.
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always @(out) begin
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if ((in === 1'bz && out !== 1'bx) ||
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(in !== 1'bz && out !== in)) begin
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$display("in (%b) !== out (%b) at %.1f", in, out, $realtime);
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pass = 1'b0;
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end
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diff = $realtime - (base + delay);
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if (diff < 0.0) diff = -diff;
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if (diff >= 0.01) begin
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$display("Incorrect buf delay at %.1f, got %.1f, expected %.1f",
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base, $realtime-base, delay);
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pass = 1'b0;
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end
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end
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// Check that the bufif0 output has the correct value and changed at the
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// correct time.
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always @(outif0) begin
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if (ctl) begin
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if (outif0 !== 1'bz) begin
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$display("outif0 (%b) !== 1'bz at %.1f", out, $realtime);
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pass = 1'b0;
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end
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end else if ((in === 1'bz && outif0 !== 1'bx) ||
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(in !== 1'bz && outif0 !== in)) begin
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$display("in (%b) !== outif0 (%b) at %.1f", in, outif0, $realtime);
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pass = 1'b0;
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end
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diff = $realtime - (base + delay);
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if (diff < 0.0) diff = -diff;
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if (diff >= 0.01) begin
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$display("Incorrect bufif0 delay at %.1f, got %.1f, expected %.1f",
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base, $realtime-base, delay);
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pass = 1'b0;
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end
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end
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function real min(input real a, input real b);
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if (a < b) min = a;
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else min = b;
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endfunction
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initial begin
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// $monitor($realtime,,out,outif0,, in,, ctl);
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pass = 1'b1;
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rise = 1.1;
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fall = 1.2;
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ctl = 1'b0;
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// x -> 0 (fall)
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in = 1'b0;
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delay = fall;
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base = $realtime;
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#2;
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// 0 -> 1 (rise)
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in = 1'b1;
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delay = rise;
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base = $realtime;
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#2;
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// 1 -> x (min(rise, fall))
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delay = min(rise, fall);
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in = 1'bz;
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base = $realtime;
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#2;
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// x -> 1 (rise)
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in = 1'b1;
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delay = rise;
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base = $realtime;
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#2;
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// 1 -> 0 (fall)
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in = 1'b0;
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delay = fall;
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base = $realtime;
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#2;
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fall = 1.0;
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// 0 -> x (min(rise, fall))
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in = 1'bx;
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delay = min(rise, fall);
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base = $realtime;
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#2;
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// x -> z (min(rise, fall))
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ctl = 1'b1;
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delay = min(rise, fall);
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base = $realtime;
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#2;
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// z -> x (min(rise, fall))
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ctl = 1'b0;
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delay = min(rise, fall);
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base = $realtime;
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#2;
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fall = 1.2;
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// x -> z (min(rise, fall))
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ctl = 1'b1;
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delay = min(rise, fall);
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base = $realtime;
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#2;
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if (pass) $display("PASSED");
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end
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endmodule
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