69 lines
1.4 KiB
Verilog
69 lines
1.4 KiB
Verilog
`ifdef __ICARUS__
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`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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`endif
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module top;
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reg pass;
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wire [2:-1] vec1;
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wire [2:-1] vec2;
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wire [2:-1] vec3;
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wire [2:-1] vec4;
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wire [2:-1] vec5;
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wire [2:-1] vec6;
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assign vec1 = 4'bxxxx;
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assign vec2 = 4'bxxxx;
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assign vec3 = 4'bxxxx;
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assign vec4 = 4'bxxxx;
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assign vec5 = 4'bxxxx;
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assign vec6 = 4'bxxxx;
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`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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assign vec1[1'bx] = 1'b1;
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assign vec2[1'bx:0] = 1'b1;
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assign vec3[0:1'bx] = 1'b1;
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assign vec4[1'bx:1'bx] = 1'b1;
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assign vec5[1'bx+:1] = 1'b1;
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assign vec6[1'bx-:1] = 1'b1;
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`endif
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initial begin
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pass = 1'b1;
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if (vec1 !== 4'bxxx) begin
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$display("Failed vec1, expected 4'bxxxx, got %b", vec1);
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pass = 1'b0;
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end
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if (vec2 !== 4'bxxx) begin
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$display("Failed vec2, expected 4'bxxxx, got %b", vec2);
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pass = 1'b0;
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end
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if (vec3 !== 4'bxxx) begin
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$display("Failed vec3, expected 4'bxxxx, got %b", vec3);
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pass = 1'b0;
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end
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if (vec4 !== 4'bxxx) begin
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$display("Failed vec4, expected 4'bxxxx, got %b", vec4);
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pass = 1'b0;
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end
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if (vec5 !== 4'bxxx) begin
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$display("Failed vec5, expected 4'bxxxx, got %b", vec5);
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pass = 1'b0;
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end
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if (vec6 !== 4'bxxx) begin
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$display("Failed vec6, expected 4'bxxxx, got %b", vec6);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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