74 lines
1.6 KiB
Verilog
74 lines
1.6 KiB
Verilog
// Released under GPL2.0
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// (c) 2002 Tom Verbeure
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module main;
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integer myInt;
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reg [13:0] myReg14;
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reg [7:0] myReg8;
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reg [31:0] myReg32;
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initial begin
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$display("============================ myReg14 = 65");
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myReg14 = 65;
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$display(">| 65|");
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$display("*|",myReg14,"|");
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$write("*|",myReg14,"|\n");
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$display(">|0041|");
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$displayh("*|",myReg14,"|");
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$writeh("*|",myReg14,"|\n");
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$display(">|00101|");
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$displayo("*|",myReg14,"|");
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$writeo("*|",myReg14,"|\n");
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$display(">|00000001000001|");
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$displayb("*|",myReg14,"|");
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$writeb("*|",myReg14,"|\n");
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$display("============================ myInt = -10");
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myInt = -10;
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$display(">| -10|");
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$display("*|",myInt,"|");
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$display(">|fffffff6|");
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$displayh("*|",myInt,"|");
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$display(">|37777777766|");
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$displayo("*|",myInt,"|");
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$display(">|11111111111111111111111111110110|");
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$displayb("*|",myInt,"|");
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$display("============================ myReg32 = -10");
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myReg32 = -10;
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$display(">|4294967286|");
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$display("*|",myReg32,"|");
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$display(">|fffffff6|");
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$displayh("*|",myReg32,"|");
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$display(">|37777777766|");
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$displayo("*|",myReg32,"|");
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$display(">|11111111111111111111111111110110|");
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$displayb("*|",myReg32,"|");
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$display("============================ myInt = 65");
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myInt = 65;
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$display(">| 65|");
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$display("*|",myInt,"|");
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$display(">|00000041|");
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$displayh("*|",myInt,"|");
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$display(">|00000000101|");
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$displayo("*|",myInt,"|");
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$display(">|00000000000000000000000001000001|");
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$displayb("*|",myInt,"|");
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end
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endmodule
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