107 lines
1.9 KiB
Verilog
107 lines
1.9 KiB
Verilog
// This module generate enable and two-bit selector for verifying a 2-to-4 decoder
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module stimulus #(parameter M = 8, T = 10) (
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output reg [1:0] sel,
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output reg en
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);
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bit [2:0] i;
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initial begin
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sel = 0;
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en = 1'bx;
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#T;
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sel = 1;
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#T;
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sel = 2;
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#T;
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sel = 3;
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#T;
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sel = 2'bxx;
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#T;
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en = 0;
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#T;
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en = 1;
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#T;
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en = 1'bx;
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#T;
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for (i = 0; i < M; i=i+1) begin
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#T;
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{sel, en} = i;
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end
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end
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endmodule
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// This module always checks that y complies with a decoding operation
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module check (input [1:0] sel, input en, input [0:3] y);
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always @(sel, en, y) begin
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if (en == 0) begin
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#1;
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if (y !== 4'b0000) begin
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$display("ERROR");
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$finish;
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end
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else if (en == 1) begin
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#1;
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case (sel)
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0: if (y !== 4'b1000) begin
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$display("ERROR");
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$finish;
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end
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1: if (y !== 4'b0100) begin
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$display("ERROR");
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$finish;
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end
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2: if (y !== 4'b0010) begin
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$display("ERROR");
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$finish;
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end
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3: if (y !== 4'b0001) begin
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$display("ERROR");
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$finish;
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end
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default: if (y !== 4'b0000) begin
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$display("ERROR");
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$finish;
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end
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endcase
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end // else
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else begin
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if (y !== 4'b0000) begin
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$display("ERROR");
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$finish;
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end
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end
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end // if
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end
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endmodule
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module test;
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parameter M = 8;
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parameter T = 10;
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parameter S = 4*M*T + 40;
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wire [1:0] sel;
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wire en;
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wire [0:3] y;
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stimulus #(M, T) stim (.sel(sel), .en(en) );
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dec2to4 duv (.sel(sel), .en(en), .y(y) );
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check check (.sel(sel), .en(en), .y(y) );
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initial begin
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#S;
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$display("PASSED");
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$finish;
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end
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endmodule
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