19 lines
346 B
Verilog
19 lines
346 B
Verilog
// Check that it is possible to declare the data type for a real type task port
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// separately from the direction for non-ANSI style port declarations.
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module test;
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task t;
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input x;
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real x;
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if (x == 1.23) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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endtask
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initial t(1.23);
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endmodule
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