40 lines
729 B
Verilog
40 lines
729 B
Verilog
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typedef enum logic [3:0] { WORD0, WORD1, WORD9='b1001, WORDC='b1100 } word_t;
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typedef union packed {
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logic [3:0] bits;
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word_t words;
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} bits_t;
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module main;
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bits_t foo;
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initial begin
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foo.bits = 'b1001;
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if (foo.bits !== 'b1001) begin
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$display("FAILED -- foo.bits=%b", foo.bits);
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$finish;
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end
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if (foo.words !== WORD9) begin
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$display("FAILED -- foo.words=%b", foo.words);
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$finish;
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end
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foo.words = WORDC;
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if (foo.words !== WORDC) begin
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$display("FAILED -- foo.words=%b", foo.words);
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$finish;
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end
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if (foo.bits !== 'b1100) begin
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$display("FAILED -- foo.bits=%b", foo.bits);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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