76 lines
1.9 KiB
Verilog
76 lines
1.9 KiB
Verilog
// Check that signed arguments to a sign cast are evaluated as self-determined.
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module test;
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reg signed [3:0] op1;
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reg signed [2:0] op2;
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reg [7:0] result;
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bit failed = 1'b0;
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`define check(val, exp) \
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if (exp !== val) begin \
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$display("FAILED(%0d). Got %b, expected %b.", `__LINE__, val, exp); \
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failed = 1'b1; \
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end
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initial begin
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// Addition tests
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op1 = 4'b1111; op2 = 3'b111;
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result = 8'sd0 + signed'(op1 + op2);
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`check(result, 8'b11111110);
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result = 8'sd0 + unsigned'(op1 + op2);
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`check(result, 8'b00001110);
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op1 = 4'b1000; op2 = 3'b011;
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result = 8'sd0 + signed'(op1 + op2);
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`check(result, 8'b11111011);
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result = 8'sd0 + unsigned'(op1 + op2);
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`check(result, 8'b00001011);
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// Multiply tests
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op1 = 4'b0101; op2 = 3'b100;
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result = 8'sd0 + signed'(op1 * op2);
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`check(result, 8'b11111100);
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result = 8'sd0 + unsigned'(op1 * op2);
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`check(result, 8'b00001100);
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op1 = 4'b0010; op2 = 3'b100;
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result = 8'sd0 + signed'(op1 * op2);
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`check(result, 8'b11111000);
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result = 8'sd0 + unsigned'(op1 * op2);
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`check(result, 8'b00001000);
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// Left ASR tests
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op1 = 4'b1010;
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result = 8'sd0 + signed'(op1 <<< 1);
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`check(result, 8'b00000100);
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result = 8'sd0 + unsigned'(op1 <<< 1);
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`check(result, 8'b00000100);
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op1 = 4'b0101;
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result = 8'sd0 + signed'(op1 <<< 1);
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`check(result, 8'b11111010);
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result = 8'sd0 + unsigned'(op1 <<< 1);
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`check(result, 8'b00001010);
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// Right ASR tests
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op1 = 4'b0101;
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result = 8'sd0 + signed'(op1 >>> 1);
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`check(result, 8'b00000010);
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result = 8'sd0 + unsigned'(op1 >>> 1);
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`check(result, 8'b00000010);
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op1 = 4'b1010;
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result = 8'sd0 + signed'(op1 >>> 1);
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`check(result, 8'b11111101);
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result = 8'sd0 + unsigned'(op1 >>> 1);
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`check(result, 8'b00001101);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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