30 lines
473 B
Verilog
30 lines
473 B
Verilog
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// This tests SystemVerilog packages. Make sure that typedef
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// names work.
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package p1;
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localparam step = 5;
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task foo(output int y, input int x);
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y = x + step;
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endtask // foo
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endpackage
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module main;
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import p1::foo;
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int y, x;
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initial begin
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x = 5;
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foo(y, x);
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if (y != 10) begin
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$display("FAILED -- x=%0d, y=%0d", x, y);
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$finish;
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end
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$display("PASSED");
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$finish;
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end // initial begin
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endmodule // main
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