17 lines
329 B
Verilog
17 lines
329 B
Verilog
// This tests end labes (test should pass compilation)
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Iztok Jeras.
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module test ();
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// error counter
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bit err = 0;
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initial
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begin : dummy_label
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if (!err) $display("PASSED");
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end : dummy_label
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endmodule : test
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