21 lines
774 B
Verilog
21 lines
774 B
Verilog
// This just tests the compiler accepts the syntax. It needs to be improved
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// when deferred assertions are supported.
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module test();
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integer i = 1;
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initial begin
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assert #0 (i == 1);
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assert #0 (i == 0);
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assert #0 (i == 1) else $display("Check 3 : this shouldn't be displayed");
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assert #0 (i == 0) else $display("Check 4 : this should be displayed");
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assert #0 (i == 1) $display("Check 5 : this should be displayed");
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assert #0 (i == 0) $display("Check 6 : this shouldn't be displayed");
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assert #0 (i == 1) $display("Check 7 : this should be displayed");
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else $display("Check 7 : this shouldn't be displayed");
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assert #0 (i == 0) $display("Check 8 : this shouldn't be displayed");
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else $display("Check 8 : this should be displayed");
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end
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endmodule
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