11 lines
338 B
Verilog
11 lines
338 B
Verilog
module top;
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initial begin
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#(32'hf0000000);
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$display("$simtime: ",$simtime, ", $time: ",$time, ", $stime: ",$stime);
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#(32'h10000000);
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$display("$simtime: ",$simtime, ", $time: ",$time, ", $stime: ",$stime);
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#(32'hf0000000);
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$display("$simtime: ",$simtime, ", $time: ",$time, ", $stime: ",$stime);
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end
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endmodule
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