57 lines
1.4 KiB
Verilog
57 lines
1.4 KiB
Verilog
`ifdef __ICARUS__
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`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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`endif
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module top;
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parameter pval = -2;
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reg pass = 1'b1;
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reg [14:-1] big = 16'h0123;
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reg [15:0] big_0 = 16'h0123;
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reg signed [15:0] idxs [0:1];
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reg signed [15:0] a;
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reg [4*8:1] res;
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initial begin
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/* If this fails it is likely because the index width is less
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* than an integer width. */
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a = -2;
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$sformat(res, "%b", big[a+:4]);
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if (res !== "011x") begin
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$display("Failed: &PV<> check 1, expected 4'b011x, got %s.", res);
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pass = 1'b0;
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end
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a = 0;
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idxs[0] = -1;
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$sformat(res, "%b", big_0[idxs[a]+:4]);
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if (res !== "011x") begin
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$display("Failed: &PV<> check 2, expected 4'b011x, got %s.", res);
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pass = 1'b0;
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end
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/* This should work since it is a constant value. */
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`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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$sformat(res, "%b", big[pval+:4]);
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`else
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$sformat(res, "%bx", big[(pval+1)+:3]);
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`endif
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if (res !== "011x") begin
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$display("Failed: &PV<> check 3, expected 4'b011x, got %s.", res);
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pass = 1'b0;
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end
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/* This should always work since it uses the index directly. */
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a = -1;
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$sformat(res, "%b", big_0[a+:4]);
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if (res !== "011x") begin
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$display("Failed: &PV<> check 4, expected 4'b011x, got %s.", res);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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