31 lines
721 B
Verilog
31 lines
721 B
Verilog
module top;
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reg pass;
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reg [3:0] array [1:8];
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reg signed [2:0] a;
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reg signed [127:0] b;
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reg [4*8:1] res;
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initial begin
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array [7] = 4'b1001;
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pass = 1'b1;
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/* If this fails it is likely because the index width is less
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* than an integer width. */
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a = -1;
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$sformat(res, "%b", array[a]);
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if (res !== "xxxx") begin
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$display("Failed: &A<> negative, expected 4'bxxxx, got %s.", res);
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pass = 1'b0;
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end
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b = 7;
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b[120] = 1'b1; // This should be stripped!
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$sformat(res, "%b", array[b]);
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if (res !== "1001") begin
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$display("Failed: &A<> large, expected 4'b1001, got %s.", res);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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