58 lines
1.5 KiB
Verilog
58 lines
1.5 KiB
Verilog
/*
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* Copyright (c) 2003 The ASIC Group (www.asicgroup.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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module mult58s(input [4:0] a, input signed [7:0] b, output signed [15:0] p);
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wire signed [12:0] pt;
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wire signed [5:0] ta;
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assign ta = a;
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assign pt = b * ta;
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assign p=pt;
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endmodule
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module test_mult;
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integer a,b, prod;
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wire [15:0] p;
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mult58s dut(a[4:0], b[7:0], p);
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initial begin
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for(a = 0; a < (1<<5); a=a+1 )
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for(b=-127; b<128; b=b+1)
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begin
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prod = a * b;
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#1 if(p !== prod[15:0]) begin
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$display("Error Miscompare with a=%h, b=%h expect = %0d (%h) acutal = %h",
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a[4:0], b[7:0], prod, prod[15:0], p);
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$finish;
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end
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end
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$display("PASSED");
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end
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endmodule
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