116 lines
2.9 KiB
Verilog
116 lines
2.9 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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//
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// SDW: Instantiation of Modules:
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//
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// D: Instantiate two versions of a module containing a single
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// D: resetable f/f. Reset both - then feed 1 module with a clock
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// D: and validate that the output toggles. Feed the 2nd module
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// D: with a clock and validate that the 2nd output toggles.
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//
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//
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module test_mod (reset,clka,out);
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input reset;
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input clka;
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output out;
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reg out;
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always @(posedge clka or posedge reset)
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if(reset)
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out = 0;
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else
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begin
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out = ~out;
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$display("saw a clk at %d, out is %b\n",$time,out);
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end
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endmodule
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module main();
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reg reset,clk_0,clk_1;
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wire out_0,out_1;
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test_mod module_1 (reset,clk_0,out_0);
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test_mod module_2 (reset,clk_1,out_1);
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initial
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begin
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clk_0 = 0;
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clk_1 = 0;
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#1 reset = 1;
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# 2;
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$display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\n",$time,reset,clk_0,
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clk_1,out_0,out_1);
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// Validate that both out_0 and out_1 are reset
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if(out_0)
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begin
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$display("FAILED - out_0 not reset\n");
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$finish ;
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end
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if(out_1)
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begin
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$display("FAILED - out_1 not reset\n");
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$finish ;
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end
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reset = 0;
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$display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\n",$time,reset,clk_0,
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clk_1,out_0,out_1);
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# 2;
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clk_0 = 1;
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# 2; // Wait so we don't worry about races.
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$display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\n",$time,reset,clk_0,
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clk_1,out_0,out_1);
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if(!out_0)
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begin
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$display("FAILED - out_0 didn't set on clk_0\n");
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$finish ;
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end
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if(out_1)
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begin
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$display("FAILED - out_1 set on wrong clk!\n");
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$finish ;
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end
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clk_1 = 1;
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# 2; // Wait so we don't worry about races.
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$display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\n",$time,reset,clk_0,
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clk_1,out_0,out_1);
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if(!out_1)
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begin
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$display("FAILED - out_1 didn't set on clk_1\n");
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$finish ;
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end
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if(!out_0)
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begin
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$display("FAILED - out_0 changed due to clk_0\n");
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$finish ;
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end
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$display("PASSED\n");
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$finish ;
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end
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endmodule
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