42 lines
793 B
Verilog
42 lines
793 B
Verilog
module dff (q, d, cp, sdn, cdn);
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output q;
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input cp;
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input d;
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input sdn;
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input cdn;
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reg q;
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always @(posedge cp or negedge sdn or negedge cdn) begin
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if (~sdn) q <= 1;
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else if (~cdn) q <= 0;
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else q <= d;
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end
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specify
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if (sdn && cdn) (posedge cp => (q +: d)) = (1, 1);
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(negedge cdn => (q +: 1'b0)) = (1, 1);
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(negedge sdn => (q -: 1'b1)) = (1, 1);
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endspecify
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endmodule
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module test;
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reg d, clk, set, clr;
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dff dut(q, d, clk, ~set, ~clr);
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initial begin
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d=0; clk=0; set=0; clr=0;
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$monitor($time,, "d=%b, clk=%b, set=%b, clr=%b, q=%b",
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d, clk, set, clr, q);
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$sdf_annotate("ivltests/sdf6.sdf");
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#10 d = 1;
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#10 set = 1;
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#10 set = 0;
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#10 clr = 1;
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#10 clr = 0;
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#10 clk = 1;
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#10 d = 0;
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end
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endmodule
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