44 lines
621 B
Verilog
44 lines
621 B
Verilog
module test();
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real val;
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always @(val) begin
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$display("val = %f", val);
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end
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task automatic test_task(input integer delay, input real val1, input real val2);
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real val;
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fork
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begin
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@(val) $display("val%0d = %f", delay, val);
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@(val) $display("val%0d = %f", delay, val);
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end
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begin
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#delay;
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#2 val = val1;
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#2 val = val1;
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#2 val = val2;
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end
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join
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endtask
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initial begin
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#1 val = 1.0;
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#1 val = 1.0;
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#1 val = 2.0;
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fork
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test_task(1, 1.1, 2.1);
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test_task(2, 1.2, 2.2);
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join
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fork
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test_task(1, 2.1, 3.1);
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test_task(2, 2.2, 3.2);
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join
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#1 $finish(0);
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end
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endmodule
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