45 lines
1.4 KiB
Verilog
45 lines
1.4 KiB
Verilog
/* * Copyright (c) 1999 Daniel Nelsen (dhn@qedinc.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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module main;
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reg [5:0] a ;
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reg error;
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// test ?: in continuous assignment with mix of constant
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// and non-constant inputs
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wire [3:0] val1 = a[4] ? a[3:0] : 4'd0 ;
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wire [3:0] val2 = a[4] ? 4'hf : ~a[3:0] ;
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initial begin
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error = 0;
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for (a = 0; a < 32; a=a+1 ) begin
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#1 ; // wait for change in a[] to propagate to val
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if (( a[4] && (( val1 != a[3:0] ) || ( val2 != 15 ))) ||
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( !a[4] && (( val1 != 0 ) || ( val2 != ~a[3:0] ))))
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begin
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$display( "FAILED a=%b, val1=%b, val2=%b",
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a[4:0], val1, val2 );
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error = 1;
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end
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end
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if(error == 0)
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$display("PASSED");
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end
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endmodule
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