96 lines
1.6 KiB
Verilog
96 lines
1.6 KiB
Verilog
// Check that blocking partial writes to a 2-state vector are correctly
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// handlded.
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module test;
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reg failed = 1'b0;
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`define check(val, exp) \
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if (exp !== val) begin \
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$display("FAILED. Got %b, expected %b.", val, exp); \
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failed = 1'b1; \
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end
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bit [3:0] x;
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integer i;
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initial begin
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// Immediate index
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// Within bounds
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x = 'h0;
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x[2:1] = 2'b10;
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`check(x, 4'b0100)
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// Partially oob at high and low side
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x = 'h0;
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x[4:-1] = 6'b101010;
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`check(x, 4'b0101)
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// Partially oob at low side
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x = 'h0;
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x[0:-1] = 2'b10;
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`check(x, 4'b0001)
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// Partially oob at high side
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x = 'h0;
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x[4:3] = 2'b01;
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`check(x, 4'b1000)
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// Fully oob at low side
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x = 'h0;
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x[-1:-2] = 2'b11;
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`check(x, 4'b0000)
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// Fully oob at high side
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x = 'h0;
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x[6:5] = 2'b11;
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`check(x, 4'b0000)
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// Variable index
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// Within bounds
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i = 1;
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x = 'h0;
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x[i+:2] = 2'b10;
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`check(x, 4'b0100)
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// Partially oob at high and low side
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i = -1;
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x = 'h0;
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x[i+:6] = 6'b101010;
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`check(x, 4'b0101)
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// Partially oob at low side
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i = -1;
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x = 'h0;
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x[i+:2] = 2'b10;
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`check(x, 4'b0001)
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// Partially oob at high side
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i = 3;
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x = 'h0;
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x[i+:2] = 2'b01;
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`check(x, 4'b1000)
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// Fully oob at low side
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i = -2;
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x = 'h0;
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x[i+:2] = 2'b11;
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`check(x, 4'b0000)
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// Fully oob at high side
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i = 5;
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x = 'h0;
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x[i+:2] = 2'b11;
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`check(x, 4'b0000)
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// Undefined index
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i = 'hx;
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x = 'h0;
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x[i+:2] = 2'b11;
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`check(x, 4'b0000)
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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