34 lines
689 B
Verilog
34 lines
689 B
Verilog
module main;
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wire [1:0] a2, b2;
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wire [2:0] a3, b3;
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target #(.WA(2), .WB(2)) u1 (a2, b2);
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target #(.WA(3), .WB(3)) u2 (a3, b3);
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initial begin
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$display("u1.WA=%d, $bits(u1.A)=%d", u1.WA, $bits(u1.A));
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$display("u1.WB=%d, $bits(u1.A)=%d", u1.WB, $bits(u1.B));
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if ($bits(u1.A) != 2) begin
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$display("FAILED -- $bits(u1.A) = %d", $bits(u1.A));
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$finish;
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end
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if ($bits(u2.A) != 3) begin
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$display("FAILED -- $bits(u2.A) = %d", $bits(u2.A));
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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module target
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#(parameter WA = 4, WB = 4)
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(input [WA-1:0] A, output [WB-1:0] B);
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assign B = A;
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endmodule // target
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