21 lines
442 B
Verilog
21 lines
442 B
Verilog
/*
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* This test is from PR#556.
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*
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* The output should generate signed and unsigned values
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* from -256 to 256. Also, since the $random sequence is
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* repeatable, it should generate the *same* seqnence
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* every time the program is run.
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*/
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module test_ran;
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integer i,j;
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initial
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begin
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for (j=0;j<256;j=j+1)
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begin
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i = $random % 256;
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$display ("The random number is %d",i);
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end
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$finish(0);
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end
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endmodule
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