37 lines
915 B
Verilog
37 lines
915 B
Verilog
module example;
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reg r, c, e;
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reg [4:0] a, b;
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wire d;
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assign d = ( r | ( a == b ) ) ? 1'b0 : 1'b1;
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// Change inputs at time n*100
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initial begin
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#100 r = 1'bx; a = 5'bxxxxx; b = 5'bxxxxx;
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#100 r = 1'b1; a = 5'bxxxxx; b = 5'bxxxxx;
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#100 r = 1'b1; a = 5'b00000; b = 5'b00000;
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#100 r = 1'b0; a = 5'b00000; b = 5'b00000;
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#100 $finish(0);
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end
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// Store c and e at time n*100 + 25.
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// Note that the value assigned to c is exactly the same as
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// the continuous assignment RHS for d (assigned to e).
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initial #25 forever begin
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#100
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c = ( r | ( a == b ) ) ? 1'b0 : 1'b1;
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e = d;
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end
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// Display all values at time n*100 + 50
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initial #50 forever begin
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#100
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$display( "%b,%b,%b = ( %b | ( %b == %b ) ) ? 0 : 1",
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c, d, e, r, a, b );
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end
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endmodule
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