76 lines
2.1 KiB
Verilog
76 lines
2.1 KiB
Verilog
/*
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* Copyright (c) 2002 Jane Skinner
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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// Icarus 0.6, snapshot 20020728 or snapshot 20010806
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// ==================================================
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// -- confused by complex disables
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//
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// -- to run, incant
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// iverilog tt.v
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// vvp a.out
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//
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// Veriwell
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// ========
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// -- OK
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//
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module top;
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integer loop_cntr, simple_fail, loop_fail;
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reg fred, abort;
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initial begin
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#1;
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simple_fail = 0;
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loop_fail = 0;
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fred = 0;
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abort = 1;
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#4;
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fred = 1;
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#4
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if(simple_fail) $display("\n***** simple block disable FAILED *****");
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else $display("\n***** simple block disable PASSED *****");
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if(loop_fail) $display("***** complex block & loop disable FAILED *****\n");
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else $display("***** complex block & loop disable PASSED *****\n");
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$finish(0);
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end
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// simple block disable
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initial begin: block_name
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#2;
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disable block_name;
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simple_fail = 1;
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end
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// more complex: block disable inside for-loop
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initial begin
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#2;
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begin: configloop
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for (loop_cntr = 0; loop_cntr < 3; loop_cntr=loop_cntr+1) begin
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wait (fred);
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if (abort) begin
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disable configloop;
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end
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loop_fail = 1;
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end
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end // configloop block
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if (loop_fail) $display("\n\ttime: %0t, loop_cntr: %0d",$time,loop_cntr);
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end
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endmodule
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