36 lines
741 B
Verilog
36 lines
741 B
Verilog
module top;
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reg pass;
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enum reg[0:0] { IDLE = 1'b0,
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BUSY = 1'b1
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} state, next;
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initial begin
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pass = 1'b1;
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next = IDLE;
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if (state !== 1'bx) begin
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$display("FAILED initial state, got %b", state);
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pass = 1'b0;
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end
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#1;
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state = next;
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if (state !== 1'b0) begin
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$display("FAILED idle state, got %b", state);
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pass = 1'b0;
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end
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next = BUSY;
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#1;
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state <= next;
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if (state !== 1'b0) begin
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$display("FAILED still idle state, got %b", state);
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pass = 1'b0;
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end
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#1;
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if (state !== 1'b1) begin
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$display("FAILED busy state, got %b", state);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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