31 lines
730 B
Verilog
31 lines
730 B
Verilog
module test;
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reg pass;
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reg [8*40:1] str;
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reg [15:0] v;
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initial begin
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pass = 1'b1;
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v = 2;
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$sformat(str, "%0d", (v + 2 - 1) * 1);
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if (str[8*1:1] !== "3" || str[8*40:8*1+1] !== 0) begin
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$display("FAILED 1st test, expected \"3\", got %s", str);
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pass = 1'b0;
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end
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$sformat(str, "%0d", 'd1 - 'd2 + v);
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if (str[8*1:1] !== "1" || str[8*40:8*1+1] !== 0) begin
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$display("FAILED 2nd test, expected \"1\", got %s", str);
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pass = 1'b0;
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end
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$sformat(str, "%0d", v + (-1));
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if (str[8*1:1] !== "1" || str[8*40:8*1+1] !== 0) begin
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$display("FAILED 3rd test, expected \"1\", got %s", str);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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