51 lines
1.5 KiB
Verilog
51 lines
1.5 KiB
Verilog
// This file extends the original bug test case to explore all the
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// forms of a signed right shift that are treated as special cases.
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module test;
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reg pass;
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reg [8*40:1] str;
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integer s;
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initial begin
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pass = 1'b1;
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s = 1;
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$sformat(str, "%0d", ((0 >> 1) + 1) * -1);
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if (str[8*2:1] !== "-1" || str[8*40:8*2+1] !== 0) begin
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$display("FAILED 1st test, expected \"-1\", got %s", str);
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pass = 1'b0;
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end
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$sformat(str, "%0d", ((2 >> 1) + 1) * -1);
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if (str[8*2:1] !== "-2" || str[8*40:8*2+1] !== 0) begin
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$display("FAILED 2nd test, expected \"-2\", got %s", str);
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pass = 1'b0;
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end
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$sformat(str, "%0d", ((2 >> s) + 1) * -1);
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if (str[8*2:1] !== "-2" || str[8*40:8*2+1] !== 0) begin
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$display("FAILED 3rd test, expected \"-2\", got %s", str);
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pass = 1'b0;
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end
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$sformat(str, "%0d", ((s >> 1) + 1) * -1);
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if (str[8*2:1] !== "-1" || str[8*40:8*2+1] !== 0) begin
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$display("FAILED 4th test, expected \"-1\", got %s", str);
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pass = 1'b0;
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end
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$sformat(str, "%0d", ((s >> 0) + 1) * -1);
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if (str[8*2:1] !== "-2" || str[8*40:8*2+1] !== 0) begin
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$display("FAILED 5th test, expected \"-2\", got %s", str);
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pass = 1'b0;
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end
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$sformat(str, "%0d", ((s >> 64) + 1) * -1);
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if (str[8*2:1] !== "-1" || str[8*40:8*2+1] !== 0) begin
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$display("FAILED 6th test, expected \"-1\", got %s", str);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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