31 lines
746 B
Verilog
31 lines
746 B
Verilog
module top;
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integer res;
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real rvar [1:0];
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realtime rtvar [1:0];
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wire real rnet [1:0];
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assign rnet[0] = 2.0;
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initial begin
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rvar[0] = -1.0;
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rtvar[0] = 1.0;
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#1;
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// Check the various get routines.
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$display("Real %g, Realtime %g", rvar[0], rtvar[0]);
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$display("Real as int %d, Realtime as int %d", rvar[0], rtvar[0]);
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$display("Real net %g", rnet[0]);
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$display("Real net as int %d", rnet[0]);
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// Check some put routines.
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res = $sscanf("3.5", "%f", rvar[1]);
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if (rvar[1] != 3.5) $display("Failed %%f put");
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else $display("Passed %%f put");
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res = $sscanf("4", "%d", rtvar[1]);
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if (rtvar[1] != 4.0) $display("Failed %%d put");
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else $display("Passed %%d put");
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end
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endmodule
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