23 lines
385 B
Verilog
23 lines
385 B
Verilog
// Based on pr2579479
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module main;
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supply0 gnd;
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supply1 vdd;
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wire A,B;
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tranif1 uA(gnd, A, vdd);
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tranif1 uB(A, B, vdd);
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tranif1 uC(B, vdd, gnd);
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initial begin
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#1 $display("A=%d, B=%d", A,B);
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if ((A !== 1'b0) || (B !== 1'b0)) begin
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$display("FAILED -- A=%b, B=%b", A, B);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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