23 lines
708 B
Verilog
23 lines
708 B
Verilog
module top;
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lower #(0, 0, 1) dut();
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endmodule
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module lower;
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parameter one = 0; // This should be 'sd0
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parameter two = 0; // This should be 'sd0
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parameter three = 0; // This should be 'sd1
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parameter local1 = one - two; // This should be 'sd0
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// This line is not working correctly.
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// The 1 is not considered signed!
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// local1 + 1 is giving 'd1 not 'sd1.
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parameter local2 = local1+1-three; // This should be 'sd0
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// Even this fails.
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// parameter local2 = local1+'sd1-three; // This should be 'sd0
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initial begin
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// This should be 2 < -1.
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if (2 < local2-1) $display("FAILED");
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else $display("PASSED");
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end
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endmodule
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