108 lines
2.6 KiB
Verilog
108 lines
2.6 KiB
Verilog
module top;
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reg passed;
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reg signed[31:0] m_one, m_two, zero, one, two;
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// Both argument positive.
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reg signed[31:0] rem;
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wire signed[31:0] wrem = two / one;
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// First argument negative.
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reg signed[31:0] rem1n;
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wire signed[31:0] wrem1n = m_two / one;
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// Second argument negative.
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reg signed[31:0] rem2n;
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wire signed[31:0] wrem2n = two / m_one;
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// Both arguments negative.
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reg signed[31:0] rembn;
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wire signed[31:0] wrembn = m_two / m_one;
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// Divide by zero.
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reg signed[31:0] remd0;
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wire signed[31:0] wremd0 = one / zero;
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initial begin
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passed = 1'b1;
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m_one = 32'hffffffff;
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m_two = 32'hfffffffe;
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zero = 32'h00000000;
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one = 32'h00000001;
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two = 32'h00000002;
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#1;
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// Both positive.
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if (wrem !== 32'h00000002) begin
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$display("Failed: CA divide, expected 32'h00...02, got %h",
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wrem);
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passed = 1'b0;
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end
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rem = two / one;
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if (rem !== 32'h00000002) begin
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$display("Failed: divide, expected 32'h00...02, got %h",
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rem);
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passed = 1'b0;
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end
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// First negative.
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if (wrem1n !== 32'hfffffffe) begin
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$display("Failed: CA divide (1n), expected 32'hff...fe, got %h",
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wrem1n);
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passed = 1'b0;
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end
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rem1n = m_two / one;
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if (rem1n !== 32'hfffffffe) begin
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$display("Failed: divide (1n), expected 32'hff...fe, got %h",
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rem1n);
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passed = 1'b0;
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end
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// Second negative.
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if (wrem2n !== 32'hfffffffe) begin
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$display("Failed: CA divide (2n), expected 32'hff...fe, got %h",
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wrem2n);
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passed = 1'b0;
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end
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rem2n = two / m_one;
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if (rem2n !== 32'hfffffffe) begin
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$display("Failed: divide (2n), expected 32'hff...fe, got %h",
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rem2n);
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passed = 1'b0;
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end
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// Both negative.
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if (wrembn !== 32'h00000002) begin
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$display("Failed: CA divide (bn), expected 32'h00...02, got %h",
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wrembn);
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passed = 1'b0;
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end
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rembn = m_two / m_one;
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if (rembn !== 32'h00000002) begin
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$display("Failed: divide (bn), expected 32'h00...02, got %h",
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rembn);
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passed = 1'b0;
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end
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// Divide by zero.
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if (wremd0 !== 32'hxxxxxxxx) begin
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$display("Failed: CA divide (d0), expected 32'hxx...xx, got %h",
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wremd0);
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passed = 1'b0;
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end
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remd0 = one / zero;
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if (remd0 !== 32'hxxxxxxxx) begin
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$display("Failed: divide (d0), expected 32'hxx...xx, got %h",
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remd0);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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