135 lines
3.2 KiB
Verilog
135 lines
3.2 KiB
Verilog
`begin_keywords "1364-2005"
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module top;
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reg passed = 1'b1;
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wire out, cout0, cout1;
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reg sel, in_1, in_0;
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reg pout;
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`ifdef __ICARUS__
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// This is technically incorrect for 1'bz inputs. The standard
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// states that we should produce 1'bx for that case (idiotic)!
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localparam zz_blend = 1'bz;
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`else
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localparam zz_blend = 1'bx;
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`endif
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assign cout0 = sel ? 1'bz : in_0;
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assign cout1 = sel ? in_1: 1'bz;
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assign out = sel ? in_1: in_0;
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task automatic check;
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input bit, in_1, in_0;
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input [63:0] comment;
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begin
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if (sel === 1'b1) begin
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if (bit !== in_1) begin
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$display("FAILED: %0s sel = 1'b1, expected %b, got %b",
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comment, in_1, bit);
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passed = 1'b0;
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end
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end else if (sel === 1'b0) begin
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if (bit !== in_0) begin
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$display("FAILED: %0s sel = 1'b0, expected %b, got %b",
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comment, in_0, bit);
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passed = 1'b0;
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end
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end else begin
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if (in_0 === 1'bz && in_1 === 1'bz && bit !== zz_blend) begin
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$display("FAILED: %0s sel = 1'bx/z & ins = %b, expected 1'b%b, got %b",
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comment, in_0, zz_blend, bit);
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passed = 1'b0;
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end else if (in_0 === in_1 && in_0 !== bit) begin
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$display("FAILED: %0s sel = 1'bx/z & ins = %b, expected 1'b%b, got %b",
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comment, in_0, in_0, bit);
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passed = 1'b0;
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end else if (in_0 !== in_1 && bit !== 1'bx) begin
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$display("FAILED: %0s sel = 1'bx/z & %b %b, expected 1'bx, got %b",
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comment, in_1, in_0, bit);
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passed = 1'b0;
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end
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end
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end
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endtask
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// Check the 1 case as a constant Z
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always @(cout0) begin
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check(cout0, 1'bz, in_0, "CZ 1");
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end
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// Check the 0 case as a constant Z
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always @(cout1) begin
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check(cout1, in_1, 1'bz, "CZ 0");
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end
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// Check the continuous assign
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always @(out) begin
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check(out, in_1, in_0, "CA");
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end
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// Check procedural assign.
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always @(sel, in_1, in_0) begin
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check(sel ? in_1 : in_0, in_1, in_0, "PR");
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end
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initial begin
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#1 sel = 1'b1;
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#1 in_1 = 1'b0;
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#1 in_1 = 1'b1;
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#1 in_1 = 1'bz;
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#1 in_1 = 1'bx;
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#1 sel = 1'b0;
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#1 in_0 = 1'b0;
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#1 in_0 = 1'b1;
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#1 in_0 = 1'bz;
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#1 in_0 = 1'bx;
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#1 sel = 1'bx;
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#1 in_1 = 1'b0; //
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#1 in_0 = 1'b0;
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#1 in_0 = 1'b1;
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#1 in_0 = 1'bz;
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#1 in_0 = 1'bx;
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#1 in_1 = 1'b1; //
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#1 in_0 = 1'b0;
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#1 in_0 = 1'b1;
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#1 in_0 = 1'bz;
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#1 in_0 = 1'bx;
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#1 in_1 = 1'bz; //
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#1 in_0 = 1'b0;
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#1 in_0 = 1'b1;
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#1 in_0 = 1'bz;
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#1 in_0 = 1'bx;
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#1 in_1 = 1'bx; //
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#1 in_0 = 1'b0;
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#1 in_0 = 1'b1;
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#1 in_0 = 1'bz;
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#1 in_0 = 1'bx;
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#1 sel = 1'bz;
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#1 in_1 = 1'b0; //
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#1 in_0 = 1'b0;
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#1 in_0 = 1'b1;
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#1 in_0 = 1'bz;
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#1 in_0 = 1'bx;
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#1 in_1 = 1'b1; //
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#1 in_0 = 1'b0;
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#1 in_0 = 1'b1;
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#1 in_0 = 1'bz;
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#1 in_0 = 1'bx;
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#1 in_1 = 1'bz; //
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#1 in_0 = 1'b0;
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#1 in_0 = 1'b1;
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#1 in_0 = 1'bz;
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#1 in_0 = 1'bx;
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#1 in_1 = 1'bx; //
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#1 in_0 = 1'b0;
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#1 in_0 = 1'b1;
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#1 in_0 = 1'bz;
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#1 in_0 = 1'bx;
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#1 if (passed) $display("PASSED");
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end
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endmodule
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`end_keywords
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