33 lines
677 B
Verilog
33 lines
677 B
Verilog
module main;
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function integer my_ceil;
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input number;
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real number;
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if (number > $rtoi(number))
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my_ceil = $rtoi(number) + 1;
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else
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my_ceil = number;
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endfunction
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real tck;
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parameter CL_TIME = 13125;
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wire [31:0] result1 = my_ceil( CL_TIME/tck );
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integer result2;
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initial begin
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tck = 2.0;
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result2 = my_ceil( CL_TIME/tck );
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if (result2 !== 6563) begin
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$display("FAILED -- result2=%d", result2);
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$finish;
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end
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#1 if (result1 !== 6563) begin
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$display("FAILED -- result1=%d", result1);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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