25 lines
516 B
Verilog
25 lines
516 B
Verilog
module top;
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reg pass = 1'b1;
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parameter one = 1'b1;
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parameter zero = 1'b0;
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wire [3:0] ca_tru = one ? 4'b0001 : 4'b0000;
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wire [3:0] ca_fal = zero ? 4'b0000 : 4'b0010;
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initial begin
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#1;
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if (ca_tru != 4'b0001) begin
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$display("FAILED: CA true expression (%b != 4'b0001)", ca_tru);
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pass = 1'b0;
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end
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if (ca_fal != 4'b0010) begin
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$display("FAILED: CA false expression (%b != 4'b0010)", ca_fal);
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pass = 1'b0;
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end
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if(pass) $display("PASSED");
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end
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endmodule
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