92 lines
2.3 KiB
Verilog
92 lines
2.3 KiB
Verilog
`timescale 1ns/10ps
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module top;
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reg pass = 1'b1;
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reg a, b, ci;
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wire co, s;
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adder dut(co, s, a, b, ci);
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initial begin
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// The initial value propagates in 1.6 nS.
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#1.59 check_result(1'bx, 1'bx, 1);
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#1 a = 0; b = 0; ci = 0; // 1.7
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#1.69 check_result(1'bx, 1'b0, 2);
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// Check the a => s delays.
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#1 a = 1; b = 0; ci = 0; // 1.1
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#1.09 check_result(1'b0, 1'b1, 3);
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#1 a = 0; b = 0; ci = 0; // 1.9
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#1.89 check_result(1'b1, 1'b0, 4);
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// Check the b => s delays.
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#1 a = 0; b = 1; ci = 0; // 1.2
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#1.19 check_result(1'b0, 1'b1, 5);
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#1 a = 0; b = 0; ci = 0; // 1.8
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#1.79 check_result(1'b1, 1'b0, 6);
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// Check the ci => s delays.
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#1 a = 0; b = 0; ci = 1; // 1.3
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#1.29 check_result(1'b0, 1'b1, 7);
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#1 a = 0; b = 0; ci = 0; // 1.7
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#1.69 check_result(1'b1, 1'b0, 8);
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// Check the a => s delays (state-dependent).
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#1 a = 0; b = 1; ci = 0;
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#3 a = 1; b = 1; ci = 0; // 2.0
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#1.99 check_result(1'b1, 1'b0, 9);
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#1 a = 0; b = 1; ci = 0; // 1.0
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#0.99 check_result(1'b0, 1'b1, 10);
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#1 a = 0; b = 1; ci = 1;
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#3 a = 1; b = 1; ci = 1; // 1.4
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#1.39 check_result(1'b0, 1'b1, 11);
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#1 a = 0; b = 1; ci = 1; // 1.6
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#1.59 check_result(1'b1, 1'b0, 12);
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// Check the co delay.
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#1 a = 0; b = 1; ci = 0;
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#1.49;
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if (co !== 1'b1) begin
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$display("Failed initial value for co test, %b != 1'b1", co);
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pass = 1'b0;
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end
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#0.02;
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if (co !== 1'b0) begin
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$display("Failed final value for co test, %b != 1'b0", co);
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pass = 1'b0;
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end
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#10 if (pass) $display("PASSED");
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end
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task check_result(input cur, input next, input integer num);
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begin
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if (s !== cur) begin
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$display("Failed initial value for test %0d, %b != %b", num, s, cur);
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pass = 1'b0;
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end
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#0.02;
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if (s !== next) begin
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$display("Failed final value for test %0d, %b != %b", num, s, next);
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pass = 1'b0;
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end
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end
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endtask
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endmodule
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module adder (co, s, a, b, ci);
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input a, b, ci;
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output co, s;
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assign {co, s} = a + b + ci;
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specify
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(a, b, ci => co) = 1.5;
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(ci => s) = (1.3, 1.7);
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if (b === 1'b1 && ci === 1'b0) (a => s) = (1, 2);
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if (b === 1'b1 && ci === 1'b1) (a => s) = (1.4, 1.6);
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ifnone (a => s) = (1.1, 1.9);
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ifnone (b => s) = (1.2, 1.8);
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endspecify
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endmodule
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