12 lines
329 B
Verilog
12 lines
329 B
Verilog
module top;
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parameter rval = 1.23456;
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real rlv = 1.23456;
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initial begin
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$display("Real :%g: has a width of %0d.", rlv, $bits(rlv));
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$display("Parameter real :%g: has a width of %0d.", rval, $bits(rval));
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$display("Real constant :%g: has a width of %0d.", 1.23456,
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$bits(1.23456));
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end
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endmodule
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